Hi all, I hope you enjoyed Meetup #5 and have made good progress on your designs. If you’re curious about what ESD protection looks like in an actual circuit, see the pictures below. They show the ESD structures I used in my tape out of a bandgap reference. If implementing ESD protection is new to you, I recommend trying to connect these pictures to slides 7 and 8. If this doesn’t make sense, look up “mosfet body diode”. The primary ESD is provided by the GPIO cell (here). What you see in the pictures is my secondary ESD circuitry.

@John Kustin what project is this in? I'd like to download the source files and take a look

@Taylor Barton https://github.com/johnkustin/bandgapReferenceCircuit

Thanks!

@John Kustin I couldn't actually find the esd circuitry you described in the linked repo. Is this an older version than what was submitted for tapeout?

@Jared Marchant Ah yeah sorry about that. I had done that work in a 2nd repository: https://github.com/johnkustin/caravel_user_project_analog You should be able to see them now 🙂

Great! Thank you!

@Jared Marchant Which file are you looking at? My top level integration uses  io11,io12 which is  * mprj_io[12]  io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5]  --- ** porst  * mprj_io[11]  io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4]  --- ** vbg see schematic of top level setup in this schematic view, you can se i choose the gpio_analog net instead of the gpio_nosed net. I ran LVS on this before I submitted to the shuttle, so the same should be true for the layout POV. (I really hope this is the case) As far as I know, the syntax “gpio_analog/nosed” means you can either have the esd or the noesd. This duality is shown in the diagram of the gpio cell by the two paths “pad_a_esd: see gpio diagram below Tim Edward recently made a post which includes a description of the esd and noesd versions: https://skywater-pdk.slack.com/archives/C02096M650E/p1636134941019800?thread_ts=1635268404.007400&amp;cid=C02096M650E https://skywater-pdk.slack.com/archives/C02096M650E/p1634132233060500?thread_ts=1634105500.058200&amp;cid=C02096M650E https://skywater-pdk.slack.com/archives/C02096M650E/p1632420208012400 <- here you can see the different “gpio_analog/no_esd” options in the actual layout I hope this clarifies things

Oh yes, you're correct. I misread, I thought your signals were being routed through the bare analog_io on top of the chip, but yeah if you're going through the gpio_analog you have the primary esd there. Sorry! & Thanks.

@Jared Marchant No problem! Thank you for checking 😄