Hi, I was trying to go through the basic analog tool flow and made a buffer's (and its sub-cell, the inverter ) schematic and layout. I followed the tutorials on bminch youtube channel, which were helpful. -I got a stuck on the netgen part and despite reading the tutorials , I still can't understand why LVS is failing. I have checked the circuit manually and changed my layout and schematic a few times but there must be something Im missing. I followed the example on caravel_user_project_analog and invoked netgen in batch mode ( run_lvs_buf.sh), indicating the layout extracted netlist (buf.spice) and the subckt in particular (buf), then i pointed to the xschem testbench (tb_buf2.spice) and to the subckt i want to compare (buf2), finally I pointed to the setup.tcl file (which is the one in openpdks netgen/sky130A_setup.tcl). When I look at the comparison file (attached as comp.out) I can see that netgen fails to match the subcell (inverters) and then proceeds to flatten the top level (buf), but even then it fails to match the cells. However I dont see any information on the comp.file that points to the difference, on the contrary it seems to me that both devices and nodes match. -The other thing that i dont understand is that the netlist extracted from layout shows 0 area/perim for drain/source. The dimensions also dont make a lot of sense (but they are similar to those on the caravel example). Have you found similar issues? What do you recommend? Thanks

@Tim Edwards ^

@Emanuel Caceres: Magic's extraction method can't distinguish how much of a diffusion area belongs to any specific transistor connected to it---it only records the total diffusion area shared by all transistors on any one net. So all the source/drain area gets lumped onto one device if that area is shared by multiple devices. You can use the

-d

(distributed) switch with

ext2spice

to distribute source/drain area and perimeter equally among devices. That is occasionally inaccurate but generally more realistic than lumping all areas and perimeters on one device. By far, the largest effect of the area and perimeter is from the calculation of the capacitance of the source and drain; for capacitance calculations, lumping all areas and perimeters onto one device on a net is equivalent to specifying area and perimeter individually for each device.

Thanks @Tim Edwards and @Philipp Gühring! The recommendations worked. The reason I used the schematic's testbench instead of the block under test netlist directly is because I was trying to follow the comments on the ./run_lvs_buf.sh file lines 17-23 on caravel_user_analog_project As a good practice, should I directly use the cell and avoid the testbench? Or should I only do that temporarily(until the parsing error issue is solved)?

@Emanuel Caceres: As I said, "Normally this should not affect the outcome". What I found is that when using the

.lib sky130.lib.spice tt

file, the LVS works (that is what was used in the

caravel_user_project_analog

example). That might be because netgen doesn't known how to parse a

.lib

line.

ok, thanks for the clarification! So I should keep in mind wheter i use .lib or .include and choose testbench or subckt respectively. (the reason i was avoiding the .lib is to avoid the long wait produced by ngspice reading all libraries, but that is irrelevant to netgen)