open-source-silicon.dev

<@U01U8HRHRKJ> and I are trying to figure out how to user project space digital GPIO works. We can tell that there are plenty of digital i/o pins, but are each of those a 32 bit register as seems to be indicated on this page (<https://caravel-harness.readthedocs.io/en/latest/gpio.html>) or is it just a 1 bit buffered digital pin??

<@U016EM8L91B> is probably best positioned to answer this.

<@U02D3RX63QS>:  As indicated in the document, that GPIO setup is for the one GPIO pin that belongs exclusively to the management SoC.  For the record, it uses only one bit from each of the associated memory-mapped 32-bit registers.  But that pin is not the user GPIO.  For the user GPIO, you want to look a little further down where it says "User project area GPIO".  However, it's not particularly readable and it's easier to work by example from the verification testbenches in the caravel repository.  Basically all of the testbenches follow the general procedure of configuring the user space GPIO before doing anything else.  For example, `caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c`;  you will want to have lines in the C code like `reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;` to configure the GPIO for use as a digital output pad controlled by the user project;  then since the user GPIO configuration is loaded by a serial loader, you follow the configuration settings with `reg_mprj_xfer = 1; while (reg_mprj_xfer == 1);`  to trigger the loading and to wait for it to finish before continuing with any interactions between the management SoC and the user project.

<@U016EM8L91B> so, to clarify - we are making an analog amplifier. So if we wanted to have a digital enable or power up/down or trimming bits we would use the "User project area GPIO" configured as a digital input. But say we need 3-4 trimming bits, would we need to have 3-4 digital input pads, or does each pin have a register we can read/write to?

<@U02D3RX63QS>:  If you want to write digital vectors in a convenient way, I would suggest using the management SoC's "logic analyzer", which has 128 bits of full-duplex digital I/O.  Setting the values could then be controlled from the program running on the SPI flash, via UART communication with a host if needed.  Otherwise, if you want to drive everything from external pins, then yes, you would need one pad per input bit, unless you want to implement an SPI interface (for which you'd still need four pins, but then you can control an arbitrarily large number of bits internal to the user project).