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Can anyone tell me how to solve this problem? I wa...
# ieee-sscs-dc-21q3
o
Can anyone tell me how to solve this problem? I was trying to run a simple inverter which I designed using verilog in Xilinx Vivado and I wanted to run it in openlane. The code doesn't seem to have any simulation error but for some reason when running it in openlane it's showing this error. Help is appreciated thanks!
b
Perhaps @mehdi can help.
👍 1
m
@Omiya Hassan So based on your screenshots, your module is 
inverter_ohbk4
while you are probably setting your top as 
inv_ohbk4
. see Error no such module: 
inv_ohbk4
Please try that and see if it works
o
oh thanks! it worked
but now I think I'm running into this error regarding openroad
m
Something is wrong with pdn gen. I am guessing since it is 1 inverter, then the area is so small that there are no room to create a power grid? We need to take a look at your def or gds file as well as your gds. It will give more insights I think
o
I'm sharing My design folder that generated all the runs and configs.
inverter_ohbk4_2.zip
m
I think the zip file is empty. Probably better if you could clone this somewhere so I could open it on my machine
o
b
The Openlane FAQ page is not working but previously it had a recommendation to pass small designs, that I paste below, see if it works: # configuration added to the file: ./configuration/floorplan.tcl [inside the openlane directory] set ::env(FP_CORE_UTIL) 5 # configuration added to the file: ./configuration/placement.tcl [inside the openlane directory] set ::env(PL_TARGET_DENSITY) 0.5
m
the placer diverges on designs that are really tiny like gcd. I will try to look into your link later @Omiya Hassan. Please tag me next time so I get a notification
o
@mehdi thanks alot for looking into it. I'll surely tag you next time.
@britovski thanks!, I'll try it and let you know if it worked.
@britovski I was trying to run your command link in the bash$ after mounting the openlane but somehow they were saying there's a syntax error near )
@mehdi there was an existing inverter design in the design files and I ran it and it successfully executed without any fata errors but not sure why mine one did not work.
b
@Omiya Hassan you just need to modify those lines on the configuration files (floorplan.tcl and placement.tcl) and run openlane again... you should not to run them stand alone...
o
@britovski okay thanks!
@britovski I did make changes accordingly and re-ran the whole thing again but having the same error. I'll try to do another design which is a bit larger, say a 8-bit adder and see if it has the same error.
m
Hi @Omiya Hassan I would append necessary parameters to config.tcl file of your design. Such as Add set ::env(FP_CORE_UTIL) 25 Note: Decreasing core utilization increases the area that is allocated for wires etc. (routing). So, this is related to area optimization. Feel free to try other numbers (30 for 30%, etc.)
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@Omiya Hassan you can refer to here https://github.com/efabless/openlane/tree/master/configuration for more parameters.
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@Omiya Hassan for inverter, I suspect changing core utilization won’t be enough. You need to set a fixed width and length instead letting the tools decide based on utilization. Since it is only one inverter cell, there is nothing much to spread around.
👍 1
o
@M Ceylan Morgul thanks a lot for the assistance. I'll go through a bigger design and see if it works. I'll update you on it
Thanks everyone, I seemed to get a grasp on how the openlane is working and I think I successfully ran two design files according to your suggestions.
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