Greetings Everyone! Does anyone know how to solve this issue. I have tried with different areas. By using different values for FP_CORE_UTIL, DIE_AREA = 4 mm, 25mm, also tried with PL_TARGET_DENSITY. But no luck.

I think your utilization is way too high, target somewhere around 40% and keep increasing it.

@mehdi Does it has anything to do with DIE_AREA? I mean that was not set. So I guessed that it was caused by area. So, first I set it to 1mm then 4mm and then 25mm

yes. There are 2 ways you can setup your overall area. either by specifying the target density /aspect ratio and core util or by specifying the the die area. I would suggest to try each of these two and see. Normally the documentation should be saying this 🙂

@mehdi I have tried with UTIL with both 40 and 55 (default) and varying DENSITY from 0.4 to 0.6, on 0.4 and 0.5 it says: Use a higher -density or re-floorplan with a larger core area. Given target density: 0.40 Suggested target density: 0.57 Error: or_replace.tcl, 93 GPL-0302

Can you point me to your config.mk ?

For 0.6 is gives error and shows this kind of things before error: output292 overlaps output249 output293 overlaps 23676 output294 overlaps output235 output295 overlaps 23674 output296 overlaps output277 output297 overlaps 23676 output298 overlaps output291

correct

# User config set ::env(DESIGN_NAME) multiplier53Booth   # Change if needed set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]   # Fill this set ::env(CLOCK_PERIOD) "10.0" set ::env(CLOCK_PORT) "clk"   set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl if { [file exists $filename] == 1} {    source $filename }

the issue you are having is that the area is too small. so you can fix that by either letting OR calculate that automatically or fix it manually. The overlaps errors you see above are the result of having a tight area

But I have not set any constraints for DIE_AREA which I think is unset by default. I am only playing with util and density