@User @User Hi! I think it would make sense to have a discussion next time about reset and sdc files for hierarchical designs (things like input and output delays definition or sync vs async reset and propagating

wb_rst_i

). Also, understanding the timing reports and where to find them. Could efabless walk everyone through that? I am getting a lot of related questions in private. Thanks!

Thanks for the suggestion, Mehdi. Adding @jeffdi.