Hello to all, I have one question about macro hardening.  What I would to do is to harden a few macros (SonarOnChip channels). on my top level module and then, generate a macro of the top module, which I would like to integrate with caravel harness (Chip Hardening). The question itself is, if the methodology based on hierarchical macro hardening is correct ? I suppose it is possible however I would like to be 100% sure. The top module have some extra logic next to the multiples macros of SonarOnChip channels.

Nice work @Krzysztof Herman. Please be careful and propagate your sdc constraints correctly especially input/output delays between the timing critical blocks. I would also suggest to run everything flat without hierarchies (just in case and do some comparisons between flat and hierarchical)