Hello all, we are trying to use RISC-V to execute a program by reading and writing contents through Wishbone bus. But when we tried to execute wishbone read & write from the Flash memory, it took about 250 cycles of 50MHz clock for each wb_write/read. And then we tried executing the same code from SRAM, and it took about 25 cycles of 50MHz clock for each wb_write/read. I assume that the Flash memory is connected to the processor via SPI and so time complexity increases for Parallel to serial conversion, but still 250 cycles for one wb_write is so high. Could someone explain the reason for this slow execution of the program?

I read through this several times until I think I understand what you're doing: You have a program to execute reads and writes on your user project using the Caravel management SoC. When you run that code from the SPI flash, it takes 250 core clock cycles for a single data read or write, but when you copy that code into SRAM and run it, it takes only 25 cycles for the same data read or write. The main difference is still just the difference in parallel vs. serial. The SRAM reads 32 bits in one go, whereas the SPI flash reads one bit at a time at a clock rate that's half the core clock rate, so yes, it's a lot slower. If you configure the SPI flash controller to run in QSPI + DDR mode, you'll get an 8x speedup. But it will still be slower than running the program from SRAM.

Thanks @User.