We couldn't finish the integration of our three pr...
# ieee-sscs-dc-21q3
l
We couldn't finish the integration of our three projects at top level at all. Anyway, I tried to submit my project to efabless and it didn't work at all. A precheck of an incomplete version of our chip (Chip 3 - https://efabless.com/projects/476 ) failed... I'm using analog only blocks and no schematics at all. All blocks were directly designed at layout level using Magic, extracted and simulated using ngspice. There are no top netlists for XOR checks, nor LVS checks, as there are no xschem files at all. There are no verilog files as there are no digital cells. It fails some KLayout checks, although it passes all Magic DRC checks. The individual blocks are ok. How can I fix it?
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[11/28/21 15:20:48 PST] SUBMITTED

            [11/28/21 15:25:13 PST] STARTED


            [11/28/21 15:25:15 PST] PROJECT GIT INFO
            Repository: <https://github.com/lhrodovalho/sscs-pico-afe-vco-vga.git> | Branch: main | Commit: 866a205d22fcebe62ab8fcb0774d23921f9099c0

            [11/28/21 15:25:15 PST] EXTRACTING GDS
            Extracting GDS files in: sscs_pico_chip_3

            [11/28/21 15:25:15 PST] PROJECT GDS INFO
            user_analog_project_wrapper: e63c6af88eb0653c61f739160e576601304fedf0

            [11/28/21 15:25:15 PST] TOOLS INFO
            KLayout: v0.27.3 | Magic: v8.3.220

            [11/28/21 15:25:15 PST] PDKS INFO
            Open PDKs: 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb

            [11/28/21 15:25:15 PST] START
            Precheck Started, the full log 'precheck.log' will be located in 'sscs_pico_chip_3/jobs/mpw_precheck/872ee74e-f428-400a-be9f-3ece5190f93f/logs'

            [11/28/21 15:25:15 PST] PRECHECK SEQUENCE
            Precheck will run the following checks: Manifest Makefile Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea

            [11/28/21 15:25:15 PST] STEP UPDATE
            Executing Check 1 of 11: Manifest

            [11/28/21 15:25:15 PST] MANIFEST CHECKS FAILED
            Manifest checks failed. Caravel version does not match. Please rebase your Repository to the latest Caravel master.

            [11/28/21 15:25:15 PST] STEP UPDATE
            Executing Check 2 of 11: Makefile

            [11/28/21 15:25:16 PST] MAKEFILE CHECK PASSED
            Makefile valid.

            [11/28/21 15:25:16 PST] STEP UPDATE
            Executing Check 3 of 11: Consistency

            [11/28/21 15:25:16 PST] CONSISTENCY CHECK FAILED
            caravan.spice file was not found.

            [11/28/21 15:25:16 PST] CONSISTENCY CHECK FAILED
            The user netlist and the top netlist are not valid.

            [11/28/21 15:25:16 PST] STEP UPDATE
            Executing Check 4 of 11: XOR

            [11/28/21 15:25:19 PST] XOR CHECK FAILED
            The GDS file has non-conforming geometries.

            [11/28/21 15:25:20 PST] STEP UPDATE
            Executing Check 5 of 11: Magic DRC


            [11/28/21 15:25:23 PST] MAGIC DRC CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:23 PST] STEP UPDATE
            Executing Check 6 of 11: Klayout FEOL

            [11/28/21 15:25:25 PST] KLAYOUT FEOL CHECK FAILED
            The GDS file, user_analog_project_wrapper.gds, has DRC violations.

            [11/28/21 15:25:26 PST] STEP UPDATE
            Executing Check 7 of 11: Klayout BEOL

            [11/28/21 15:25:42 PST] KLAYOUT BEOL CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:42 PST] STEP UPDATE
            Executing Check 8 of 11: Klayout Offgrid

            [11/28/21 15:25:46 PST] KLAYOUT OFFGRID CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:46 PST] STEP UPDATE
            Executing Check 9 of 11: Klayout Metal Minimum Clear Area Density

            [11/28/21 15:25:47 PST] KLAYOUT METAL MINIMUM CLEAR AREA DENSITY CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:47 PST] STEP UPDATE
            Executing Check 10 of 11: Klayout Pin Label Purposes Overlapping Drawing

            [11/28/21 15:25:49 PST] KLAYOUT PIN LABEL PURPOSES OVERLAPPING DRAWING CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:49 PST] STEP UPDATE
            Executing Check 11 of 11: Klayout ZeroArea

            [11/28/21 15:25:50 PST] KLAYOUT ZEROAREA CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:50 PST] FINISH
            Executing Finished, the full log 'precheck.log' can be found in 'sscs_pico_chip_3/jobs/mpw_precheck/872ee74e-f428-400a-be9f-3ece5190f93f/logs'

            [11/28/21 15:25:50 PST] FAILURE
            4 Check(s) Failed: ['Manifest', 'Consistency', 'XOR', 'Klayout FEOL'] !!!

            [11/28/21 15:25:50 PST] FAILED
g
Hello @User, for our design we encountered 164 FEOL violations during precheck. We then navigated to that error locations and found that those are created by an extra layer generated by Magic but that layer can only be seen in Klayout. Then we manually removed all those extra layers using Klayout and used that gds, which then overcame FEOL errors. So please use this link to open the error file https://docs.google.com/document/d/e/2PACX-1vReQ0aIlNDlg5dP4GvfhZoI_k9Idv8SxG9vV_dDJ2p1TxGln2fVXW6ogNVh6AIROlKClxZj9Iul6-xG/pub And then find which layer causes the violations for your design, then open your individual macro gds using klayout and manually remove/process the extra layers appropriately. Use this modified gds file in wrapper. This must help sorting out this issue.
l
Thanks! I'll try that.
My error is a bit worse than yours... It's a DRC rule that magic doesn't check at all. I'll have to remake some parts of the layout that has those mim capacitors. I've custom made them and thought magic would detect any DRC violation, but it just checks for metal layer DRC.
r
yes @User we also encountered the same issue. But as you said ya we relayed those capacitors.
b
@User is looking at your design. Stay tuned for some feedback.
l
If it is really spacing between the capacitors, I will just increase it and I'll have it fixed today. Even then, I still have to integrate the other designs from the other teams. And fix the remaining precheck errors. We are already three days late for 26/11 deadline...
b
Please work with @User, we may still be able to get you to the finish line...
r
@User you don't need netlists for XOR checks, It only requires your design to be in the wrapper. For netlist consistency check you can simply extract the LVS netlist from the top-level wrapper (with your designs inside) using magic and place it in the netgen folder "üser_analog_project_wrapper". You should also have a caravel folder in the directory which you can get by
git clone --recursive <https://github.com/efabless/caravel_user_project_analog.git>
l
Interesting... I didn't use this --recursive option. I think most of my mistakes are results of bad github cloning. There was no caravel folder with a simple git clone command.
r
The netlist extracted by magic is probably going to miss either vssa1 or vssa2, which you would have to include manually in the netlist
can you point me to the repo, I might be able to help. I have spent my fair share of time on these checks 😅
l
The XOR check is a comparison between the empty and the user_analog_project_wrapper. It's not working. I don't know why. The precheck job log is very inconclusive and I don't know where are the exactly the errors. Maybe this was a version problem...
r
Ok I have just run a local precheck on your project from github. It passes all checks except XOR. Let me see what's the issue
l
Is there a way to see where it is? It should be a non issue, as it is a comparison with the empty wrapper. I can't even know where are the 6 errors it says it has.
r
yes you are right is shouldnt normally be there. There are 6 metal 5 drawing rectangles on top which don't make sense. You can view the difference of XOR in the precheck results. A gds having only the diferences is generated there
l
Ah... I think I know the problem them. The pad inputs are in Metal 3. I've routed everything manually in metal 4 and 5. Instead of lowering the metal layers before entering the pad, I did it inside the pad.
r
Great. I hope that is the issue. However, if that doesn't work, you should place your analog design in the empty_project_wrapper.mag again (from the caravel user project git/mag). I have just placed your design without routing in the empty wrapper and it passes the xor check. You may need to make connections to pads again
l
I'll try. This is the last issue, then it is ready to go. Thanks!
r
no problem. let me know if something else come up
Also, I am sure you are already doing it, run the
drc style drc(full)
while laying out in magic
l
Now there are lots of Magic DRC errors I didn't see before... Almost 2000 of them. No way I can finish it soon. Sorry, @User, I won't be able to finish it. It is a serious error which I would need at least a week to finish. No finish line here for me. Until MPW4!
b
That's too bad... In any case, thanks for trying and for being a great contributor to the contest & its community!