for the first couple of items, could you please do...
# ieee-sscs-dc-21q3
j
for the first couple of items, could you please do a ‘Git Pull’ from the Workspace tab on the Project Details View? Looks like you are missing the caravel directory under the project root. Please add that to your repo.
l
https://github.com/efabless/caravel_user_project_analog I'm using this as basis for the project. I didn't properly install it. I'll try making the git project.
j
@User any progress?
l
No progress... The first try had some KLayout issues and no Magic DRC issues. After fixing the KLayout, XOR, and Manifest issues, close to 2000 Magic DRC violations appeared. I don't know why the precheck didn't show any Magic DRC failure before fixing the KLayout issues.
I was using the default Magic DRC check and my design was clean. After switching to full DRC, it showed some errors for nwell spacing for every cell I made. It seems that 5.0 V MVT devices have different nwell spacing than standard ones. I would need to convert all my devices to standard 1.8 V ones or to remake my design. I would need at least a week to finish it and the deadline was last Friday. More than that, the other teams on this chip didn't send me their designs and this chip had only my design. I think it's better to try MPW4, if it is still available, of course.
j
what do you mean by full DRC ? you really only need to pass the MR DRC deck to submit on the shuttle.
we would really like to get you on this shuttle. perhaps we can take a look?
l
Of course. I'll provide some info. Just a sec.
j
is your repo current?
l
First mpw precheck:
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STDOUT: {{FAILURE}} 4 Check(s) Failed: ['Manifest', 'Consistency', 'XOR', 'Klayout FEOL'] !!!
Fifth mpw precheck attempt:
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[11/29/21 09:45:15 PST] FAILURE
            1 Check(s) Failed: ['XOR'] !!!
9th attempt:
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[11/29/21 12:24:25 PST] FAILURE
            1 Check(s) Failed: ['Magic DRC'] !!!
The Manifest, consistency and Klayout precheck failures I fixed by updating the caravel folder. Later, I used the caravel lite empty wrapper, placed my design there and rerouted its top level. So, the XOR precheck failure was solved. Then the Magic DRC violations appeared.
My design is really simple. It is a low noise amplifier made with pseudo-resistors and capacitive feedback, such as this.
But I replaced the single ended OTA by a fully differential OTA made with inverters, like this one.
Each inverter block layout is like this. It didn't have any DRC issue using the default Magic DRC settings. But, after I had problems with the MPW precheck, I switched to the complete DRC option in Magic and those violations appeared.
j
can you do a ‘Git Pull’ on the Project Detail tab on the EF platform?
l
Again?
Done.
@User, if you give me some time, I think I can fix these DRC issues. How much time can you give me? We're already past the deadline by almost a week.
@User MPW precheck succeeded!
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[12/01/21 15:20:39 PST] SUCCESS
            All Checks Passed !!!