so all of my clocks are shifting in frequency and ...
# silicon-validationa
Andrew Zonenberg
01/13/2022, 2:44 PMso all of my clocks are shifting in frequency and phase
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Tobias Strauch
01/14/2022, 1:55 PMPlease forgive me my bullish inquiry.
PS: No proposal intended, but if I’m right, FPGA PLL (e.g. Xilinx) can be reprogrammed on the fly (without partial reconfig).
Have a great time! Cheers.
a
Andrew Zonenberg
01/14/2022, 4:50 PMThat's what I mean, using the DRP. It's still PR in my mind, although I'm not actually loading a full partial bitstream through the ICAP
Andrew Zonenberg
01/14/2022, 4:50 PMThe DRP is essentially a local ICAP that only writes to the config memory of the PLL
Andrew Zonenberg
01/14/2022, 4:50 PMbut as you're still changing bits at run time that were originally written by the bitstream, I consider it a form of PR
Andrew Zonenberg
01/14/2022, 4:51 PMThat's how I'm doing it. But since you are dynamically changing frequency and phase (the FPGA is a Xilinx, Spartan-7) relative to the parameters that static timing was done with at the time you created the bitstream, you have to be very careful to not introduce timing violations that won't be seen by STA
t
Tobias Strauch
01/15/2022, 11:56 AMSo you created a low-cost, but yet very efficient test-setup, congratulations.
Regarding my proposal:
1) The test frequency will\can remain constant, at a lower bound, let’s say 20MHz.
2) You could make the duty cycle adjustable and find out its minimum high time by playing with the constraints during a new synthesis and/or STA run.
3) During in-system-test the duty-cycle can then be modified from 50/50 all the way down to the minimum value, which is indicated by the STA report.