We only change the 1.8V nominal domain feeding the DUT core

DUT core is VCCD[12] in this diagram right? https://github.com/efabless/caravel/blob/main/docs/source/_static/power_domain_splits.svg I haven’t gone through this in detail, so it could be totally wrong, but I assumed the pad IO cells were on VCCD=1.8V [1]. Assuming this is correct, and since the IO goes through the control block, I figured the cell doing the level shifting is likely there [2] but as one shmoos VCCD1 relative to VCCD, the delay of that path (from pin to SRAM input) is going to slow down as the VCCD-VCCD1 increases, and the different bits in the bus will slow down by differing amounts. And that difference in path delay could explain the frequency dependance of the test. [1] So maybe there are level shifters on the PCB to do the 3.3V to 1.8V conversion but those are fixed gain as VCCD doesn’t move in this experiment. [2] https://github.com/efabless/caravel/blob/main/verilog/rtl/gpio_control_block.v I was assuming cell, sky130_fd_sc_hd__einvp_8, did it via the TE pin but I haven’t looked inside it.

This chip is not using Caravel. It predates MPW1

Oh, got it. I didn’t know this was a non-MPWx design.

Yeah they have test chips on the various MPWs as well