Have anyone encountered the following violations after P&R in Innovus/Openlane? @User @User Any ideas how to fix them? * Verify - Connectivity - UnConnPin Violations ( 1000 ) Net VGND FE_DBTC3_Tile_X3Y3_E2BEG_5_/*VNB* False : No   Layer : pwell   Bounds (100.425, 561.935) (100.595, 562.105) (-> for all power nets I think) … Verify - Overlap - Overlap Violations ( 1000 ) Blockage of Cell *FILLER*_91589 & Blockage of Cell Tile_X2Y4_LUT4AB/Inst_LUT4AB_switch_matrix/_4240_ False : No   Layer : M1   Bounds (807.300, 866.575) (808.220, 866.745) … Regular Wire of Net Tile_X1Y1_LUT4AB/Inst_LUT4AB_switch_matrix/_0321_ Actual: 0.0000 Required:    0.0000 Type:  Antenna Area Ratio False : No   Layer : M4   Bounds (574.730, 94.870) (575.730, 95.870) Regular Wire of Net Tile_X3Y2_W2BEGb[1] Actual: 0.0000 Required:    0.0000 Type:  Antenna Area Ratio False : No   Layer : M5   Bounds (703.530, 299.210) (704.530, 300.210) Regular Wire of Net Tile_X0Y2_B_O_top Actual: 0.0000 Required:    0.0000 Type:  Antenna Area Ratio False : No   Layer : M6   Bounds (455.590, 146.890) (456.590, 147.890) … Regular Wire of Net Tile_X1Y2_LUT4AB/Inst_LUT4AB_switch_matrix/_0757_ Actual: 1.4200 Required:    1.6000 Type:  Minimum Width False : No   Layer : M6   Bounds (802.360, 111.800) (826.640, 113.220) * From the layout view, it looks fine e.g., overlap between VGND and VNB pins (pwell) or the width of M6 wires are 1.6, but not sure what cause those violations?

@Nguyen Dao Best join #cadence-innovus and ask there L:)

@Nguyen Dao Is this in innovus?

yes, from innovus

@Nguyen Dao can you send a def+lef+lib so I can check what is the issue. I can't tell from your report (I have not seen these issues on my blocks)

@mehdi Just uploaded at https://github.com/FPGA-Research-Manchester/FABulous-SKY130/tree/main/common

thanks, I will try to get back to you later today (I am kind of swamped)

how did you remove it? manually in virtuoso/innovus?

in the lef file

can you send me that modified file?

yes I remember in the skywater hs lib, the std cells' LEF has mcons OBS on the top VPWR rails and bottom VGND rail, and after Innovus places these std cells, the mcons from adjacent rows will have overlap issues

@Nguyen Dao I think you need to remove these:

OBS
    LAYER li1 ;
      RECT 0.000000 -0.085000 4.140000 0.085000 ;
      RECT 0.000000  2.635000 4.140000 2.805000 ;
      RECT 0.565000  1.815000 0.895000 2.635000 ;
      RECT 0.635000  0.085000 1.310000 0.470000 ;
      RECT 0.695000  0.650000 1.915000 0.655000 ;
      RECT 0.695000  0.655000 2.805000 0.825000 ;
      RECT 0.695000  0.825000 0.915000 1.465000 ;
      RECT 0.695000  1.465000 1.345000 1.645000 ;
      RECT 1.135000  1.645000 1.345000 2.460000 ;
      RECT 1.585000  0.260000 1.915000 0.650000 ;
      RECT 2.085000  0.085000 2.430000 0.485000 ;
      RECT 2.600000  0.260000 2.805000 0.655000 ;
      RECT 2.860000  1.495000 3.990000 1.665000 ;
      RECT 2.860000  1.665000 3.145000 2.460000 ;
      RECT 3.325000  1.835000 3.540000 2.635000 ;
      RECT 3.715000  0.085000 3.955000 0.760000 ;
      RECT 3.720000  1.665000 3.990000 2.460000 ;
    LAYER mcon ;
      RECT 0.145000 -0.085000 0.315000 0.085000 ;
      RECT 0.145000  2.635000 0.315000 2.805000 ;
      RECT 0.605000 -0.085000 0.775000 0.085000 ;
      RECT 0.605000  2.635000 0.775000 2.805000 ;
      RECT 1.065000 -0.085000 1.235000 0.085000 ;
      RECT 1.065000  2.635000 1.235000 2.805000 ;
      RECT 1.525000 -0.085000 1.695000 0.085000 ;
      RECT 1.525000  2.635000 1.695000 2.805000 ;
      RECT 1.985000 -0.085000 2.155000 0.085000 ;
      RECT 1.985000  2.635000 2.155000 2.805000 ;
      RECT 2.445000 -0.085000 2.615000 0.085000 ;
      RECT 2.445000  2.635000 2.615000 2.805000 ;
      RECT 2.905000 -0.085000 3.075000 0.085000 ;
      RECT 2.905000  2.635000 3.075000 2.805000 ;
      RECT 3.365000 -0.085000 3.535000 0.085000 ;
      RECT 3.365000  2.635000 3.535000 2.805000 ;
      RECT 3.825000 -0.085000 3.995000 0.085000 ;
      RECT 3.825000  2.635000 3.995000 2.805000 ;
  END
END sky130_fd_sc_hd__a2111o_1

Thanks @mehdi, yes it works. but still couple of errors remain which I have no clue why? … Regular Wire of Net Tile_X4Y1_LUT4AB/JS2BEG[0]                    Actual: 0.0000 Required:    0.0000 Type:  Antenna Area Ratio          False : No   Layer : M4   Bounds (198.450, 350.550) (199.450, 351.550)                                        Regular Wire of Net UserCLK Actual: 0.0000 Required:    0.0000 Type:  Antenna Area Ratio          False : No   Layer : M6   Bounds (853.490, 446.090) (854.490, 447.090) … Regular Wire of Net Tile_X5Y3_OPA_I3 Actual: 1.4200 Required:    1.6000 Type:  Minimum Width           False : No   Layer : M6   Bounds (386.380, 748.550) (387.800, 754.940)

@Nguyen Dao did you manage to get past this error?

Those sounds like antenna repair issues. In your flow scripts, you should define an antenna cell to fix those. Innovus should be able to fix antenna by using layer assignment. I will need to check your designto see what is the issue

I use sky130_fd_sc_hd__diode_2 and jump wires option (I think) for antenna fixing but seems not all of them can be fixed(?). How about UnConnPin Violations? looks like VPB/VNB pins are defined as nwell/pwell type/layer and these layers don’t seem to be recognized in Innovus as a routing/connectible layer?

There are no external pins for vnb/vpb. The wells are connected using a tap cell. Did you place that?

I’m using this cell sky130_fd_sc_hd__tapvpwrvgnd_1, is that the right one?

yes

But not sure why they’re unconnected. I set this for power connections: globalNetConnect VPWR -type pgpin -pin VPWR -inst * globalNetConnect VPWR -type tiehi -pin VPWR -inst * globalNetConnect VGND -type pgpin -pin VGND -inst * globalNetConnect VGND -type tielo -pin VGND -inst * globalNetConnect VPWR -type pgpin -pin VPB -inst * globalNetConnect VGND -type pgpin -pin VNB -inst * -> any missing?

this is unnecessary in point :

globalNetConnect VPWR -type pgpin -pin VPB -inst *
globalNetConnect VGND -type pgpin -pin VNB -inst *

they are the grey columns

@wenbo can you share our lef/lib files

These are the lef and lib files we used before, it seems like when we were using Innovus with sky130hd lib, pwell and nwell layers are not added to the tech lef, and we were using the std cell lef that does not have VNB/VPB defined for each cell

Thanks @wenbo, Also have you also tried this sky130 pdk (not the s8) in Virtuoso?

yes, but I only streamed in std cell's gds from this sky130 pdk, the tech lib, drc/lvs rule decks are still from s8