@User mentioned he has an issue with lef not matching lib for the pins nwell/pwell, but I’m not sure what exactly is going on - seems like #97 is closed and #98 looks like it’s probably fixed already

@User that’d be awesome. I’m a complete noob when it comes to the silicon side, but happy to hack up fixes on the code level

Hi @User, seems you have played also with Cadence Innovus/Virtuoso, can you share the skywater techfile with us? Or any ideas how to stream in the gds?

@User @User shared his lib in bug #288 if that helps

There's like a million channels on this slack space

Have anyone encountered the following violations after P&R in Innovus/Openlane? @User @User Any ideas how to fix them? * Verify - Connectivity - UnConnPin Violations ( 1000 ) Net VGND FE_DBTC3_Tile_X3Y3_E2BEG_5_/*VNB* False : No   Layer : pwell   Bounds (100.425, 561.935) (100.595, 562.105) (-> for all power nets I think) … Verify - Overlap - Overlap Violations ( 1000 ) Blockage of Cell *FILLER*_91589 & Blockage of Cell Tile_X2Y4_LUT4AB/Inst_LUT4AB_switch_matrix/_4240_ False : No   Layer : M1   Bounds (807.300, 866.575) (808.220, 866.745) … Regular Wire of Net Tile_X1Y1_LUT4AB/Inst_LUT4AB_switch_matrix/_0321_ Actual: 0.0000 Required:    0.0000 Type:  Antenna Area Ratio False : No   Layer : M4   Bounds (574.730, 94.870) (575.730, 95.870) Regular Wire of Net Tile_X3Y2_W2BEGb[1] Actual: 0.0000 Required:    0.0000 Type:  Antenna Area Ratio False : No   Layer : M5   Bounds (703.530, 299.210) (704.530, 300.210) Regular Wire of Net Tile_X0Y2_B_O_top Actual: 0.0000 Required:    0.0000 Type:  Antenna Area Ratio False : No   Layer : M6   Bounds (455.590, 146.890) (456.590, 147.890) … Regular Wire of Net Tile_X1Y2_LUT4AB/Inst_LUT4AB_switch_matrix/_0757_ Actual: 1.4200 Required:    1.6000 Type:  Minimum Width False : No   Layer : M6   Bounds (802.360, 111.800) (826.640, 113.220) * From the layout view, it looks fine e.g., overlap between VGND and VNB pins (pwell) or the width of M6 wires are 1.6, but not sure what cause those violations?

@User one cool approach could be to fork this and add support for your bistream generator: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/make.py

@User for a first try, you should try this: https://github.com/m-labs/VexRiscv-verilog/blob/master/VexRiscv_Lite.v

<!channel> welcome to our new channel members 🙂 Do feel free to tell the channel about your interests!

@User Use this test for the vexriscv - https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/minimal

@User https://github.com/lnis-uofu/SOFA/tree/master/FPGA1212_QLSOFA_HD_PNR/modules/verilog

Hi <!channel> We’ve just done our implementation for the first version of FABulous FPGA with sky130 PDK and Cadence Innovus. The fabric consists of 1440 LUT4s (180x CLBs) and 180 LUT5s (45x RegFiles) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version. You can check it out at https://github.com/FPGA-Research-Manchester/eFPGA---RTL-to-GDS-with-SKY130 Please feel free to ask any question/comments.

... Did you have to ping the entire channel?

@User What about using the open source tools for it?

We’ve tried with the openlane but got stuck at routing, but sure we’ll get back to it for the next version

@User https://github.com/efabless/openlane/issues/278

@User Did you use vcs for your verification? Are you getting compile errors with

libs.ref/sky130_fd_sc_hd/verilog/primitives.v

@User yes, I used Synopsys tools to verify our 1st taped-out eFPGA-RiscV chip in TSMC 180nm. I haven’t done with sky130 but we will do it soon. What errors are you dealing with?

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People here might find this post interesting, from Xilinx's CTO - https://www.linkedin.com/pulse/chips-alliance-fpga-interchange-format-ivo-bolsens/?trackingId=D2msEW1%2FThmTehF86lCZ2Q%3D%3D

https://dl.acm.org/doi/abs/10.1145/3519599 - An Optimized GIB Routing Architecture with Bent Wires for FPGA -- The experimental results show that the GIB architecture with length-4 wires can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product compared to the VTR CB-SB architecture with length-4 wires. After exploring mixed wire types, the optimized GIB architecture can further improve the delay by 16.4% and area-delay product by 17.1% compared to the CB-SB architecture with length-4 wires.

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Hello All, I am Abhishek, a 4th-year UG student at the Indian Institute of Information Technology Dharwad, which is situated in Karnataka, India. Professionally, I am interested in Digital Design and Verification, RTL Design and Synthesis, and Computer Architecture. Recently, I came across a hackathon organized by Design and Verification Conference & Exhibition India, 2022, in which they are organizing a hackathon on Accelerating AI on FPGA. It is strictly open to students only. I am actively looking for teammates to participate in this hackathon. The last date to register is July 14, 2022. Links for the hackathon: https://dvcon-india.org/invite-for-hackathon/ My LinkedIn: https://www.linkedin.com/in/heyshakya/ My GitHub: https://github.com/heyshakya Regards, Abhishek

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Hi Folks, Did someone install the F4PGA toolchain into ARM base Ubuntu 22.04? I am looking for the proper “environment.yml” file for create conda environment. I would just follow https://f4pga-examples.readthedocs.io/en/latest/getting.html# and changed x86_64 to ARM base conda to setup, but cannot create xc7 env. Thanks.

I have built and installed the F4PGA toolchain on my MAC M1 of Arch64 Ubuntu by UTM, then succeeded to download into Arty-A7 to confirm the bit file. For someone who is interested in it, have just summarized all procedures on the following URL. https://jun1okamura.medium.com/build-and-install-the-fossi-fpga-toolchain-f4pga-on-the-a[…]5?source=friends_link&amp;sk=c36cdc5bf5616d4ac6a5c728179447b3 Enjoy! and let me know any feedback.

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