Hi all, I added a first version of a "how to run" documentation that might have some typos or inaccuracies. So, I'd appreciate it, if someone took a look and told me what to modify/add/remove. https://github.com/efabless/caravel/blob/develop/README.md & https://github.com/efabless/caravel/blob/develop/openlane/README.md.

will do

export PDK_ROOT=<The place where the installed pdk resides>

Please explain which directly is actually the PDK_ROOT. Is it the open_pdks? Is it open_pdks/sky130 ? Is it open_pdks/sky130/sky130A ?

@Philipp Gühring: Maybe specifying a branch & a commit would be better, right?

Yes

But the thing is we don't want to force openlane on people. So, maybe I should add pdk building to the caravel Makefile, and leave the openlane part for the user?

Well, then just offer that script and say that people can use it to get up and running easily, but that they can also do it differently.

Okay, I'll go with that. Thank you!

@Loester F. Botelho provided me with this script which I have improved slightly:

@Amr Gouhar This is a lot better, bravo.

@Amr Gouhar I think when you make your design a macro inside the wrapper there will be considerations for the power grid.

@tnt: Yes, I forgot to mention the

pdn.tcl

. I'll add that. Thank you!

If you want the top level to handle the straps, you might need

DESIGN_IS_CORE

in the macro to not generate straps on layer 5. You might also need

set ::env(GLB_RT_MAXLAYER) 5

(and even possibly add

met5

obstructions because TritonRoute take the

MAXLAYER

more like a guideline than an actual rule and will still route stuff on

met5

if it feels like it)

I can't understand the 2 options in here: https://github.com/efabless/caravel/blob/develop/openlane/README.md

Either you do step (1) and (2) ... or just step (2) and you put all your verilog directly in

user_project_wrapper

with no hierarchy.

maybe I'm too tired but I still don't get it

AFAIK you can modify user project wrapper as long as : • The pins stay where they are. That's the connection to the rest of the system and whatever you do, it shouldn't change their position / order

I have 5 pre-hardened macros. Any idea which option I should use?

How do those connect upstream / between themselves ?

I have some verilog that gets instantiated by user_project_wrapper that muxes between them

and that works ?

what do you mean works?

does it build sucessfully ?

I can harden all 5 macros + the harness with openlane rc4

Well, lucky you I guess 😅 . My general take is that trying to do any "verilog" (ie. anything that will require standard cells) directly in the

user_project_wrappers

ends up being a bit weird because it will generate a standard cell grid in that giant area. So the approach I would have taken would probably have been to have a 6th pre-hardened macro that contains all the muxing and exposes all the pins to go both upstream and to the 5 other macros. And then in the top level wrapper purely do wiring.