@User: It would not be my intention to make the pad input unreadable when the pad is configured for output. It is too late for an easy fix (the GPIO control block has been hardened and added to layout which was hand-routed) but I'm sure it can be done. I'll take a look at it. The example user project had only very simple I/O operations on the user side, so the issue didn't come up in the testbenches.

I've still not managed to get a signal from a pad to the user area. But could be doing something wrong. Take a look at this https://github.com/mattvenn/multi-project-harness/blob/eb7b26de4f6beb5c721c409c29597170013689ff/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v#L37 and see if you think it should work

@Matt Venn: Looking at the verilog for the GPIO pad control logic, it should always have a valid signal on the input line to the user project area whenever the management SoC cedes control of the GPIO to the user project. I looked at your code but didn't see anything obviously wrong, so I would have to clone your repo and debug.