open-source-silicon.dev

How are the power and ground routed from `user_project_wrapper` to `user_proj_example`?
They both have the `vccd*, vdda*, vssd*, vssa*` connections, but these signals don't connect to any gates. The actual power connections in `user_proj_example` are VPWR and VGND, but show up as floating in the extracted abstract `user_project_wrapper/runs/user_project_wrapper/results/magic/user_project_wrapper.spice`
```+ wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i mprj/VPWR mprj/VGND user_proj_example```

I'm not sure this is finalized yet. There was some change yesterday but don't think they are final yet.

General idea is that the `user_proj_example`  exposes contacts on `met4` and doesn't use `met5` at all (so no horizontal straps). Then when the PDN grid is generated in `user_project_wrapper` during the drawing of all the horizontal `met5`  straps, every time it goes over a `met4` exposed contact by the macro, it adds a via down.

Of course that relies on the fact you have large enough grid in your project so that large contacts are exported to span the pitch between contacts ...

<@U016PTY0C2E> I don't think caravel/user_project_wrapper LVS is possible until the power is connected.