open-source-silicon.dev

Am I correct that the current Caravel design can only accommodate a single bus master, the RISC-V core, and that adding a second bus master on the Wishbone bus such as a DMA controller is not feasible?

There was some discussion about this previously. Because of time limitations they only included a single-master crossbar, but in theory there's nothing preventing it from being done

would just require some restructuring of the bus and a lot of verification

A simple multiplexed bus arbiter would be a great addition for high bandwidth data processing cores.

Seems to me, that multi-master bus support, and user available CPU interrupt inputs are two essential general purpose SoC features missing in Caravel.

Now, would probably be the time to solidify what functionality will or will not be included in MPW2.

<https://arxiv.org/abs/2105.13256|OpenSerDes: An Open Source Process-Portable All-Digital Serial Link>
In the last decade, the growing influence of open source software has necessitated the need to reduce the abstraction levels in hardware design. Open source hardware significantly reduces the development time, increasing the probability of first-pass success and enable developers to optimize soft...