Where can I find the spice data for the following subckts used in the chip_io cell of caravel?

sky130_ef_io__com_bus_slice_10um
sky130_ef_io__com_bus_slice_1um
sky130_ef_io__com_bus_slice_20um
sky130_ef_io__com_bus_slice_5um
sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um
sky130_ef_io__corner_pad
sky130_ef_io__disconnect_vccd_slice_5um
sky130_ef_io__disconnect_vdda_slice_5um
sky130_ef_io__gpiov2_pad_wrapped
sky130_ef_io__vccd_lvc_clamped2_pad
sky130_ef_io__vccd_lvc_clamped_pad
sky130_ef_io__vdda_hvc_clamped_pad
sky130_ef_io__vddio_hvc_clamped_pad
sky130_ef_io__vssa_hvc_clamped_pad
sky130_ef_io__vssd_lvc_clamped2_pad
sky130_ef_io__vssd_lvc_clamped_pad
sky130_ef_io__vssio_hvc_clamped_pad

Mostly here: https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl

@Ahmed Ghazy Thanks, one step closer! Now I just need the cdl/spice for the subckts referenced in sky130_ef_io.cdl*.* Namely

sky130_fd_io__top_gpiov2
sky130_fd_io__top_ground_hvc_wpad
sky130_fd_io__top_ground_lvc_wpad
sky130_fd_io__top_power_hvc_wpadv2
sky130_fd_io__top_power_lvc_wpad

I found the verilog, gds, etc. but no spice/cdl.

@Mitch Bailey: Those are unfortunately converted but not yet released. We're (+ @Amr Gouhar) working with @Tim 'mithro' Ansell to get verifiable PRs to work so we can update the libraries at a more rapid rate...

@Ahmed Ghazy Thanks for the reply. Running regression test with the new version of magic now. When I get the spice for the pads, hopefully I'll be able to check the whole chip. BTW, the gate level verilog for simple_por does not match the gds. Do you know who's in charge of that block?

As far as I understand, @Tim Edwards mentioned that it is currently impossible to accurately extract the IO pads using magic, so it's probably only possible currently to blackbox the IO pads. Regarding

simple_por

, it's an analog circuit that Tim designed; I believe https://github.com/efabless/caravel/blob/develop/ngspice/simple_por/simple_por.spice is the reference netlist, but he can confirm. The verilog GL netlist is not accurate and is just there for simulation purposes.

@Mitch Bailey: I was getting some success in running LVS on the GPIO cell by using (in magic)

gds flatglob *__example_*
gds flatten true
gds read sky130_fd_io__top_gpiov2.gds
load sky130_fd_io__top_gpiov2
select top cell
expand
extract do local
extract no all
extract unique
extract all
ext2spice lvs
ext2spice

The "flatglob" is flattening all these cells with "example" in the name, which don't appear in the schematic hieararchy anyway. But the layout around these is separating nwells and deep nwells from the devices over them and causing magic grief when extracting. So flattening them makes the extraction go much better. The two (?) remaining issues with LVS on the pad cells is (1) there are metal resistor

short

devices in the schematic that are extracted as

sky130_fd_pr__ res_generic_m(1,2,3,...)

by magic. The extracted devices are intentional, and the netlists need to be changed. Unfortunately, the

short

device is used for any metal resistor, and in some cases the same schematic subcell corresponds to either a

res_generic_m1

or a

res_generic_m2

in the layout, so those need to be teased apart in the schematic. (2) The grounds are shorted together through the substrate and magic does not currently have a way to fake a separation of the substrate into independent regions.

@Tim Edwards Thanks for the hints. @Ahmed Ghazy

simple_por

is referenced in

verilog/gl/caravel.v

. Are you sure it's ok to remove it?

@Mitch Bailey: The RTL version is the one being referenced, right? He removed the GL version.

@Amr Gouhar I'm not that familiar with verilog, but I'm assuming that

verilog/gl/caravel.v

is intended to reference

verilog/gl/simple_por.v

. Is it possible to mix gl and rtl verilog and then use the result for LVS?

@Mitch Bailey: The RTL version is the one referenced and included here: https://github.com/efabless/caravel/blob/develop/verilog/rtl/caravel_netlists.v#L77, for simulation. For LVS, you can read in the reference netlist I linked above (https://github.com/efabless/caravel/blob/develop/ngspice/simple_por/simple_por.spice) for the schematic side.