Hope this is is the right place to post this. I wrote a small tool to generate PLL configurations for the provided PLL in the caravel management soc. I've written it based on my limited understanding of how it works, so it might not be accurate. I'd love for someone who knows how this works to look it through and let me know if anything is wrong or can be improved. Issues and PRs are very welcome! https://github.com/kbeckmann/caravel-pll-calculator

@Tim Edwards would be great if you could sanity check this

@Konrad Beckmann: The only problem is that the code is assuming a

clkout90_conf[m]

that doesn't exist. There is only one feedback divider, because there is only one ring oscillator to bounce up the frequency to. Your output has only one feedback divider value listed, but that's hiding the

clkout90_conf[m]

value that was computed. Your second example will have 72MHz on output2, not 88MHz, because it will be 16 * 9 / 2.

Nice! I started playing around with PLL calcs for Ice40 done as constant functions in Verilog. Still some kinks to work out, but it appears to give the correct results: https://github.com/RAPcores/fpga-hal/blob/main/src/pll.v I wonder if it would be worth wrapping the Caravel PLL this way for better UX and constant propagation. E.G. you can specify timing in (nanos/pico)seconds and through constant prop the frontend should be able to convert to the correct clock ticks automatically.

Thanks for the review @Tim Edwards, this is exactly the kind of feedback I was hoping for 😄 . Truth is that I thought about this but somehow forgot to implement it fully. It's fixed now.

Great! Thanks for coding up the computations. It's something I should have done but just did by hand for the various testbenches I ran.