any ideas when this will be fixed?
# caravel
m
any ideas when this will be fixed?
@donn @Manar Abdelatty @Tim Edwards
ping
t
If the GL simulation of the caravel management SoC is verified by itself, then there's not whole lot of reason to run the GL netlist of the management SoC. The testbenches may not be set up to distinguish between GL within the user project and RTL everywhere else. You would probably have to force the right include statements to be invoked. If the goal is to confirm gate-level communication to and from the management SoC, then you will need to wait until we have valid gate level netlists for the SoC. I'm not sure how the GL netlists of the managment SoC are suposed to fit in with the "lite" repository. I'll bring up the topic at today's staff meeting.
m
Thanks Tim. Yes I just want to run the GL versions of my testbenches
but the GL netlists are out of date
t
If it's just a matter up pushing the latest GL netlists from caravel to caravel_user_project, then I'll ping Manar and Jeff about it.
m
great
bump @Tim Edwards just checked on mpw-two-c and it's still broken for the built in io_ports test running SIM=GL make
@Klas Nordmark here's the thread
and any news on this @Tim Edwards?
k
Thanks for the headsup! Won't spend too much time on it for the moment at least then
m
Ping @Tim Edwards @Manar Abdelatty
Would be great to get this resolved
m
@Matt Venn Working on it. For now, you can simulate your GL with caravel's RTL.
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