I'm just re-running through the submission process...
# caravel
m
I'm just re-running through the submission process to make a video, and now when I harden user project wrapper, the io pins are all out of place! I didn't notice until I ran the checker and the xor failed. I'm still trying to work out what introduced the issue, because I've not changed any config apart from config.tcl for user_project_wrapper, and just the normal stuff.
m
@Matt Venn Betweeen
mpw-two-a
and
mpw-two-b
, the irq pins were added to the wrapper. You need to update your verilog to include the irq pins.
m
I'm pretty sure my verilog is up to date. I'm not totally sure how the xor process works. I notice there is an empty gds in the caravel submodule. Could that be out of sync with the mpw checker? I just updated the mpw checker but I haven't updated the caravel submodule
m
If your submodule is still at
mpw-two-a
, then the
pin_order.cfg
is out of date and your hardened wrapper doesn't have the correct placement for the irq pins.
m
aha
thanks
@Manar Abdelatty, no that's not it. the previous design I hardened with the same setup passes with the pins in the correct places
and I checked the caravel submodule RTL and it has the irqs
do the pins get placed evenly around the edge or is there some file that sets the positions?
hm, I think it's because I'm doing this:
just setting the output always enabled
and then oeb get's completely optimised out of user_project_wrapper
and no pins ever get placed for oeb
now trying a non zero assignment
image.png
but post synth netlist & hardened macro still lack io_oeb
nothing in yosys logs about it being optimised out
funny that other signals don't also dissapear. like the irq.
ok, I try re-harden and leave io_oeb floatingb
leaving it floating I works
ah maybe this is to do with that there is no synthesis done for upw
so I can't do an assignment here
ok, I did actually know this from last time but forgot.
putting io_oeb control inside my module and making the assignment there works as expected