The tests provided under the verilog/dv folder are...
# caravela
Anmol
05/14/2021, 12:18 PMThe tests provided under the verilog/dv folder are specific to "counter" example or it should work for any design?
t
Tim Edwards
05/14/2021, 1:01 PMThey are specific to the counter, as Matt says, but there are general principles represented there for communicating with the logic analyzer, starting up the management processor and configuring the GPIO state, etc.,
a
Anmol
05/14/2021, 2:21 PMFor my design, I need only one 1-bit input and an analog output pin. To check if my design is working well on caravel or not, what would be your suggestion? How can I do that?
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Tim Edwards
05/14/2021, 10:11 PMWrite a basic verilog behavioral model for the circuit. It does not need to be an analog model, just something where you can see the output pin swing in the testbench to confirm that the GPIO is configured correctly and the analog circuit is driving the output and not conflicting with anything.
a
Anmol
05/14/2021, 10:38 PMThankyou Sir! I will try it.
Anmol
05/20/2021, 11:13 AMSir! I am using only the GPIO's connected to the user area i.e. io_in[23] and analog_io[16]. I have written the verilog behavioural model for my design but I am unble to verify my design using testbench. I have got the precheck done successfully. Is it necessary to verify design before proceeding further?
t
Tim Edwards
05/20/2021, 1:18 PMIf you want the chip to work, then yes.