@Tim Edwards could you verify?

pinging @Tim Edwards

Definitely the CSB line on the SPI should be avoided; random toggling on the SPI lines could cause bad things to happen, although hitting the right sequence of signals by accident would be pretty low probability. For other lines, I would just ask people to consider what they might need from the management SoC. If they have no need for Tx/Rx functions, then those pins would be okay to use---but that would then preclude the ability to connect the UART back to the FTDI chip and use "print" statements in the C code which could then be read back over USB, which is a pretty important debugging tool. The JTAG pin is completely unused for now, just reserved for when we get a DFT-ready version of the management SoC done (a version of which went on MPW-one and just needs to be tested and verified). For MPW-two, add MPRJ_IO[36:37] to that list because I have reserved those for use to connect to the SPI flash IO2 and IO3 lines, which allows the SPI flash to run in quad modes, which can get the read rate up to around 50MHz, supposedly. Again, if fast routines aren't needed on the management SoC, then those pins would be free for user use. So yes, I think your recommendations are good, to let users know to use only MPRJ_IO[35:8] unless they are really in need of additional GPIO resources, because every "reserved" pin lets the management SoC do something which could potentially be useful to the user.