Hi Matt,
is it possible to feed Three 32-bit data ...
# caravelm
Manikandan Nagarajan
06/16/2021, 2:25 AMHi Matt,
is it possible to feed Three 32-bit data simultaneously from management segment to user design? If so how to handle wbs_stb_i and wstrb inthe user_project_example?
Kindly share your suggestions..
Thankyou
m
Matt Venn
06/16/2021, 9:42 AMwell wishbone data is 32 bit wide, so you couldn't just do it with that.
Matt Venn
06/16/2021, 9:42 AMbut you could maybe use the logic analyser as another data bus
Matt Venn
06/16/2021, 9:43 AMmaybe putting 64 bit extra data on logic analyser, then use wishbone as normal and in your design when you do a wishbone read, fetch the extra 64 bits of the LA at the same time
m
Manikandan Nagarajan
06/16/2021, 11:02 AMThanks Matt for the suggestions..can we skip wishbone interface without connecting to my design..is it allowed for the shuttle?if so can I simply leave wishbone signals unaltered in the user proj example?
m
Matt Venn
06/16/2021, 11:03 AMyes, just don't connect them
m
Manikandan Nagarajan
06/16/2021, 11:07 AMThank you so much
Manikandan Nagarajan
06/16/2021, 11:12 AMOne more problem it is generating when I am doing make , when i try to instantiate my submodules inthe user project yosys throws error as "cell is not the part of design". Have you faced this kind of issues?
m
Matt Venn
06/16/2021, 11:14 AMhave you added the files to uprj_netlists ?
m
Manikandan Nagarajan
06/16/2021, 11:18 AMYes I did
m
Matt Venn
06/16/2021, 11:20 AMwhere is your repo, and what commands are you running exactly
m
Manikandan Nagarajan
06/16/2021, 12:02 PMI am still doing the things locally not yet commited in git..I have done my design and kept in user_proj_example inthe place of counter. The top module I used needs one sub module and I instantiated it and kept the submodule file in the same folder that is verilog/rtl. I started to do make user_proj_example, since I replaced the design .during that I got error like that..
Manikandan Nagarajan
06/16/2021, 2:27 PMIMG_20210616_195520.jpg
Manikandan Nagarajan
06/16/2021, 2:28 PMSorry for the delayed response..this is what the screen shot of error produced for the above mentioned problem...
m
Matt Venn
06/16/2021, 2:29 PMSorry I don't have time to help debug screenshots. If you post your repo I can take a look
m
Manikandan Nagarajan
06/16/2021, 2:30 PMOk I will share soon..
🙌 1
Manikandan Nagarajan
06/16/2021, 3:57 PMI fixed that error..that was due to non inclusion of the submodule in config.tcl. I will commit the project ASAP. in between while hardening user_proj_example during clock tree synthesis process it shows error that Error when finding -clock_nets in DB! Error :or_cts.tcl ,57 UKN-0000
Have you faced anything like this?
m
Matt Venn
06/16/2021, 4:00 PMI'd imagine your clock setup in the config.tcl doesn't match your design
m
Manikandan Nagarajan
06/16/2021, 4:33 PMThanks for the suggestion. I will check.
2 Views