Hi my design repo is , https://github.com/MSPDUTTA/Subservient_SOC/tree/main/verilog/rtl , when I am trying to do "make verify-io_ports" I am receiving the below error:

U have to include ur files into user_project_netlist file available in verilog/rtl/

Thanks for the fix. After including my rtl files in place of user_project_example , which I have updated to my git repo , I see as below: any suggestions how to resolve ?

I think that this needs to be run on the user_proj_example.v, not your design - Configures MPRJ lower 8-IO pins as outputs - Observes counter value through the MPRJ lower 8 IO pins (in the testbench) The counter is the user_proj_example design