open-source-silicon.dev

I need to create my own digital PLL to achieve higher frequencies than the base 50MHz system clock. Following the model in the caravel repo I get
```ERROR: Module `\sky130_fd_sc_hd__einvn_8' referenced in module `\delay_stage' in cell `\delayenb0' is not part of the design.```
The component exists, why can't I use it?

<@U017FJJJ8P2> This may be a really dumb suggestion, but is the back slash in the module name supposed to be there?

The backslash isn't there in the verilog code, only in the error message

<@U017FJJJ8P2> Are you able to post your verilog code? Your `STD_CELL_LIBRARY` is set to `sky130_fd_sc_hd`, correct?

Yes STD_CELL_LIBRARY is set, and the code is simply a clone of the ring oscillator code from the caravel harness.

FWIW, I ran a copy of `digital_pll` on openlane `2021.09.30_02.12.16` and ran into an undefined clock error.
```create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable```