Hi all, Is there a chance for the amount of avail...
# caravel
a
Hi all, Is there a chance for the amount of available I/O to be increased? And it would be great to get a chip without Caravel's padframe, so we can use our own padframe? I cant use the Caravan ones because I need to connect other remaining pins to my own GPIO, but the noesd pins are too thin for my own Drivers and resistance is too high. Also it would be great if we could remove the mgmt soc, to save some area. For my project I need additional 2mm^2 that is apparently busy by the mgmt soc.
t
Currently we don't have any I/O tested and known good other than the ones provided by SkyWater, so those will be the only ones available in the near term. There are several people who are testing new I/O pad designs, so eventually we should be able to expand the offering. My initial goal for the caravan chip was a "mix and match" style of choosing your own I/O cells. I am still working toward this goal. The ChipIgnite program will have an additional "open frame" version without the SoC that is simply the padframe and some related infrastructure. The initial version of that will have a pin-compatible padframe but that would include six or seven additional GPIO that you could make use of. Down the road, a combination of the open frame layout and user-selectable I/O means that you can do pretty much whatever you want. It just takes a bit of time and effort to get there.
a
Currently we don't have any I/O tested and known good other than the ones provided by SkyWater, so those will be the only ones available in the near term. There are several people who are testing new I/O pad designs, so eventually we should be able to expand the offering.
I am working on my own GPIO cells, currently planning to tape it out for MPW-5. But by "amount of I/O" I meant just count of the pads. This is big deal, because for SDRAM I already need like 45 pins, and there is just not enough + I will need A LOT OF I/O for other features I wanted: SerDes (at least 6 pins) and Flash/SD controller (7 pins).
My initial goal for the caravan chip was a "mix and match" style of choosing your own I/O cells. I am still working toward this goal.
My only wish is that the Caravan's NOESD pins are bigger, so I can just use my I/O Drivers.
It just takes a bit of time and effort to get there.
I understand! I appreciate all the effort that goes in everything!