open-source-silicon.dev

<@U016EM8L91B> Not sure if it's been covered elsewhere, but will MPW5 support per project configuration of GPIOs using `user_defines.v/gen_gpio_defaults.py` ?

If you change defaults, let me know, so I can do a final review of the layout and make sure the system is working.  It was in place for MPW-four but there were no projects with a custom GPIO defaults definition.

Great! My aim is to configure the GPIOs that way, and keep the management engine in reset (I'm currently only using it to configure the GPIOs)

I have questions about modifying `user_defines.v`
1. Can you please confirm the value to set to is `GPIO_MODE_USER_STD_ANALOG` for analog projects with direct connections to pads?
2. `user_defines.v` is defined under the caravel project submodule which isn't updated when I push to my forked repo. Is there a custom location to put it within my project's repo to ensure it's picked up when the final chip is generated?

<@U01AH2JULR2>:  Yes, `GPIO_MODE_USER_STD_ANALOG` is the correct mode for analog signals connected to a GPIO.  Your custom version of the file should be in your `caravel_user_project/verilog/rtl` directory.

<@U01FYLU6TKP>:  I am pretty sure that we don't have any testbenches testing the case where a user project is running with the management SoC held in reset, so be sure that you have a top-level testbench that demonstrates that it works as expected.

<@U016EM8L91B> I've been running test benches for Microwatt with the mgmt SOC in reset, and they look ok. That reminds me to do a full gate level simulation though (I've mostly run partial gate level sim considering how slow it is)