Hi, I am about to put a VCO analog circuit into caravel for MPW5 tapeout. However, my VCO has an analog port "Vctrl" which is supposed to take in an analog voltage (anything between 0.4V up to 1.3V approx) in order to generate an output frequency that is proportional to this Vctrl. My question is, does Caravel have Analog input pins at all, or just digital? Thanks

Yes. All of the GPIO pins support both analog and digital signals. Analog signals must be limited from 0V to VDDIO (nominally 3.3V), and band-limited to 50MHz. The Caravan chip is meant to accommodate analog signals outside of that spec (mainly high voltage, negative voltage, or high frequency). Your control signal is perfectly well suited to connect to the GPIO pin. On the user wrapper, connect to the

analog_io

pins, and note that due to a different indexing system,

analog_io[0]

corresponds to GPIO 7 (that is, you are not allowed to use the lowest six GPIOs for analog signals). The management SoC program that initializes the GPIOs should set the GPIO mode for that pin to analog (configuration word

0x000a

otherwise known as

GPIO_MODE_USER_STD_ANALOG

).

just to double check Tim, so you can use analog signals all the way up to pin38?

Great, now in terms of frequency coming out, what's the max frequency that I can drive out of Caravel pins? This one would be a digital signal toggling at relatively high speed. The output of my VCO can reach higher than 3GHz according to extracted post-layout sims, which surely will be too much to drive out through the pads, hence I will need to add frequency dividers, however, what's the max frequency that the Caravel pins can drive out? That way I can divide down the frequency by the appropriate amount. Thanks

See Tim's answer above - 50MHz

ah ok I missed that. Thanks

@User maybe you can add that to the maximum ratings? https://caravel-harness.readthedocs.io/en/latest/maximum-ratings.html

@User: The analog pins are slightly restrictive: You cannot use the first 7 I/Os or the last 2 for analog, because those pins are shared with critical management functions (debug, housekeeping SPI, UART, and flash QSPI). All the other GPIO (so that's 29 of them, total) can be used for analog.

Hi @User, I'm still a bit confused by which analog pins I should use, looking at the pins in the

user_analog_project_wrapper

I see some are called gpio_analog[x] while other are called io_analog[x], you mentioned I should use

io_analog

but then I noticed that in the example

user_analog_project_wrapper

you connected the outputs of the example_por blocks to gpio_analog[] pins and not to io_analog[] pins. I'm trying to ensure I use the correct pins for my VCO inputs and outputs (whether it's io_analog[] pins or gpio_analog[] pins, or io_in[] pins, etc...) and also I want ensure I set the io_oeb[] correctly. Could you please have a look at the attached Schematic picture and let me know if I'm correct in my usage of pin types: - vctrl is the analog control voltage for the VCO --> I have connected it to

io_analog[0]

- vsel0/1/2/3 are digital 1.8V inputs to turn on/off some switches on current mirrors to have multiple bias current modes --> I have connected them to

io_in[0]

to

io_in[3]

. Since I assume io_in[x] are for digital input signals. Is this correct? - out_div128_buf and out_div256_buf --> These are the VCO output frequency divided by 128 and 256 in order to get below the 50MHz max output frequency of the output pads. I have tied them to

io_analog[1]

and

io_analog[2]

. Correct? Regarding the

io_oeb[]

, do I need to care about these, given the pin connectivity mentioned above? Thanks

Avoid using

io_analog

pins unless you have analog signals that are high voltage (> 3.3V), negative voltage, or high speed (> 50MHz digital or equivalent analog bandwidth). As soon as you connect something to those lines, you are entirely responsible for all ESD circuitry to protect your circuits. You could, for example, connect your VCO undivided output (buffered) to one of those pads.

gpio_analog

is what you want to use for the slow (< 50MHz) speed signals. For digital, avoid channels 0 to 7 except as a last resort (if you run out of signals to connect to). They have duplicate use by the management SoC for the housekeeping SPI and UART, and so are connected to other things on the development board that will just make it harder for you to test your own circuit.

Thanks @User, makes sense. How about

io_clamp_low[]

and

io_clamp_high[]

, I noticed in the example

user_analog_project_wrapper

(the one with the 2 example_por s) all

io_clamp_low

are tied to

vssa1

and

io_clamp_high[2:1]

are also tied to

vssa1

, but

io_clamp_high[0]

is tied to

io_analog[4]

, why is that? What should I do with these pins in my

user_analog_project_wrapper

, should I tie them ALL to vssa1? (I posted this question somewhere else but I removed it to avoid duplication)

If you are not adding your own independent power supply through any of the three pads that have the clamps, then you should either leave them floating or tie them both to ground. Either solution should be adequate.