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What does the `reg_spi_enable = 1` specifically do...
# caravel
h
What does the 
reg_spi_enable = 1
specifically do? I am seeing some dv tests (la_test2, wb_port) inside the caravel_user_project using this statement while the others (io_ports, la_test1) do not.
t
After MPW-two, with the processor being a separate entity, I defined a handful of bits that need to be memory-mapped in the processor, that tell the housekeeping module what systems are enabled or disabled. The 
reg_spi_enable
signal can be used to disable the housekeeping SPI, which is the proper thing to do if your user project needs to make use of GPIO pins 1 to 4, which are normally used by the housekeeping SPI. The housekeeping SPI must be enabled by default, so setting it to 1 should be non-functional.
Although, come to think of it, the zeroth bit is "SPI disable", so setting it to 1 disables the housekeeping SPI, which makes sense for those user project validation tests that need to test user access to all of the GPIOs, including the ones usually reserved for the housekeeping SPI.
h
@User then why is 
reg_spi_enable = 1
commented out here: https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/io_ports/io_ports.c#L49? This test uses GPIO pins 1 to 4 and the housekeeping spi should have been disabled.
@User can you tell more about this?
m
Hi @User, sorry for the late reply. I actually don't know why it's enabled, I'll investigate it.
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