Hello, does anybody now why Wishbone interface goes X? It happens, after all Wishbone operations in my C code are completed. Since I use the Wishbone clock, my design goes X as well. I encountered this problem in GL simulation, this does not happen in RTL simulation.

I've seen gl code that added fixed low output from a macro that had unconnected output in rtl. This same signal was shared with another macro which might cause X output.

@User I have noticed some issue in GL with caravel .. After adding Pull-up on pullup(mprj_io[3]); Now My GL flow is working https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1649629638190519

Thanks for your answers. I saw that post but my X's are coming much later than 2 us. I have already "assign mprj_io[3] = 1'b1;" in my test bench. My X's are coming after the Wishbone communication is finished.

@User are you using OpenRAM SRAM in your design?

No there is no OpenRAM SRAM in my design

@User @User Did someone create an issue with the pullup so that it will get fixed?

@User they do have the specific io pad asserted in their testbench. However, it is quite easy to miss it while merging changes with your repo to update to the latest tag.

@User But it seems that a pullup should be used to prevent this problem? It doesn't hurt to have it if it isn't used.

@User were you able to solve this issue?

@User No, I could not. I tried to add dummy Wishbone read & write in while(1), it seems promising but I could not figure out completely

Yes for some reason the

wb_clk_i

is also getting XXX for me in the GL simulation