Hi all, I have a layout with a disconnected pin that corresponds to a disconnected input wire in the Verilog top-level. The disconnected pin appears in my extracted Spice netlist, but then when comparing the two, Netgen says there’s no matching pin in the extracted netlist, while it finds the pin in the Verilog netlist. Is there some difference in how Netgen handles disconnected pins in Spice vs Verilog netlists, or anything that would explain this behavior?

Yes, quite likely. I am working on the issue that Matt mentioned above related to ground pins---these are produced by Magic because it extracts the substrate in all cells for purposes of parasitics. The problem is that parasitics are not LVS-friendly, and neither is dropping a substrate node where it doesn't need to be for LVS. But there are other possible ways to get extra pins in the netlist, so post an example if you'd like me to look into it.