@User @User Someone correct me if I'm wrong, but I'm thinking that the current default LVS setup in

flow.tcl

or

caravel/Makefile

will only check the top level of the gate level verilog. Undefined cells are treated as blackboxes with only the pins being checked. This may be ok if each level is hardened, verified separately, and placed as a macro, but otherwise how are the sub-hierarchies verified?

We generally expect that everything below the top level is hardened and verified. However, I do generally prefer that everything should be checked down to the transistor level unless (1) there are issues with extraction like with the GPIO cell, or (2) checking a large block takes a huge amount of time and compute cycles, like the management SoC. I think the current setup makes way too much use of abstracted cells.