Hello all I m trying to correctly run LVS using batch netgen open-source-silicon.dev #verification-be

Hello all, I'm trying to correctly run LVS using b...

Jorge Marin

12/29/2021, 4:29 PM

Hello all, I'm trying to correctly run LVS using batch netgen and the SKY130 setup file on a custom-designed cell. The LVS check fails, the number of cells and nets matches and i can't understand the meaning of the error. I'm attaching the netlists, the .mag and the LVS out put, I hope someone here can give me some clues on how to read the comp.out file and solve this issue. I'm using the following command to run netgen: "netgen -batch lvs DFF_v3p1.spice DFF_v3p1_xschem.spice [project_folder]/open_pdks/sky130/sky130A/libs.tech/netgen/sky130A_setup.tcl" p.s.: Since i'm not sure how to run LVS with subck netlists, I commented the magic-generated subcircuit statement manually. I'd really appreciate if anyone could take a look at this!

comp.out DFF_v3p1.spice DFF_v3p1_xschem.spice DFF_v3p1.mag DFF_v3p1.ext

Jorge Marin

12/29/2021, 4:33 PM

What I can't understand is why the comp.out file claims NET mismatches (from what I see, they look identical) and what is the meaning of the DEVICE mismatch:

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DEVICE mismatches: Class fragments follow (with node fanout counts): Circuit 1: DFF_v3p1.spice |Circuit 2: DFF_v3p1_xschem.spice --------------------------------------------------------------------------------------- Instance: sky130_fd_pr__nfet_01v813 |Instance: sky130_fd_pr__nfet_01v8MN_NIN1 (1,3) = (14,5) | (1,3) = (14,3) 2 = 5 | 2 = 5 4 = 14 | 4 = 14 | Instance: sky130_fd_pr__nfet_01v812 |Instance: sky130_fd_pr__nfet_01v8MN_NIN (1,3) = (14,3) | (1,3) = (14,5) 2 = 2 | 2 = 2 4 = 14 | 4 = 14 ---------------------------------------------------------------------------------------

Mitch Bailey

12/29/2021, 4:41 PM

Your first nfet in the layout has a source net (1) with 14 connections and a drain net (3) with 5 connections, while the schematic has 14 and 3 respectively. The 14 connections are most likely the ground because the bulk net (4) also has 14 connections. Just from this, it looks like the drain of the nfets in the layout corresponding to MN_NIN1 and MN_NIN in the schematic are reversed.

Jorge Marin

12/29/2021, 6:46 PM

tricky one, thanks for the hint @User!

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