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<@U017X0NM2E7> I'm trying to get CVC going in openlane using GDS. (`MAGIC_EXT_USE_GDS=1`). I had to ...
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a
@User I'm trying to get CVC going in openlane using GDS. (
MAGIC_EXT_USE_GDS=1
). I had to make a small fix to openlane so it would read from the gds.spice (vs lef.spice), but I'm now stuck because CVC can't find models for the pfet/nfets. I see some pretty detailed spice modules in the PDK, but CVC doesn't seem to like them (is the CDL format a subset of the spice format?). Also not sure if those models are overkill for this.
m
Hey @User. CVC needs mos devices (start with M) in the netlist. This is the 
spi2cdl
script that I use to convert X-devices in 
*.gds.spice
to cdl.
Copy code
#! /bin/bash
  
awk '
/^X.*__diode.*=/ {
        print "D" $0;
        next;
}
/^X.*__special_[^ _]*fet.*=/ || /^X.*__.fet.*=/ || /^X.*__esd_.fet.*=/ {
        print "M" $0;
        next;
}
/^X.*__pnp_.*=/ {
        print "Q" $0;
        next;
}
/^X.*__cap_mim_.*=/ {
        print "C" $0;
        next;
}
/^X.*__cap_var.*=/ {
        bulk = $4;
        $4 = "";
        print "C" $0, "$SUB=" bulk;
        next;
}
/^X.*__res_.*=/ {
        bulk = $4;
        $4 = "";
        print "R" $0, "$SUB=" bulk;
        next;
}
 {
        print $0;
}' $1
Something like 
spi2cdl <module>.gds.spice > <module>.cdl
This is the 
run_cvc
script that I use to run cvc with the openlane file structure under docker.
Copy code
#! /bin/bash

export DESIGN_NAME=$1
export finishing_tmpfiles=$DESIGN_NAME/runs/cvc/tmp/finishing
export finishing_reports=$DESIGN_NAME/runs/cvc/reports/finishing
export finishing_results=$DESIGN_NAME/runs/cvc/results/finishing
export PDK=sky130A

if [[ ! -f $finishing_tmpfiles/$DESIGN_NAME.cdl ]] ; then
        spi2cdl $finishing_results/$DESIGN_NAME.gds.spice > $finishing_tmpfiles/$DESIGN_NAME.cdl
fi

if [[ ! -f $finishing_tmpfiles/$DESIGN_NAME.power ]] ; then
        awk '
        $1 == "input" || $1 == "inout" {
                if ( NF == 3 ) {
                        $2 = $3 $2;
                }
                if ( $2 ~ /^vss/ ) {
                        print $2, "power 0.0";
                } else if ( $2 ~ /^vcc/ ) {
                        print $2, "power 1.8";
                } else if ( $2 ~ /^vdd/ ) {
                        print $2, "power 3.3";
                } else { 
                        print $2, "input min@0.0 max@1.8";
                }
        }' ../verilog/gl/$DESIGN_NAME.v | \
                sed 's/;//' > $finishing_tmpfiles/$DESIGN_NAME.power
fi      
        
export SCRIPTS_DIR=/openlane/scripts
                        
cvc $SCRIPTS_DIR/cvc/$PDK/cvcrc.sky130A
It includes a call to 
spi2cdl
. The models to cvc should be in 
OpenLane/scripts/cvc/sky130A/cvc.sky130A.models
but there may be a few missing. Please let me know if you have other questions. CDL (circuit definition language) is Calibre's flavor of spice that it uses for LVS. Have you completed device level LVS? You should be able to run with 
flow.tcl -design <design> -lvs -gds <gdsfile> -net <gl_verilog>
You'll probably need to add the included gate level verilog to 
config.tcl
using 
LVS_EXTRA_GATE_LEVEL_VERILOG
and any non-standard spice libraries with 
LVS_EXTRA_STD_CELL_LIBRARY
. Also, the latest flow requires 
LVS_INSERT_POWER_PINS=0
if you're using an already powered netlist.
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