Hi all, is there a way to get Netgen to ignore power pins (so that you can run LVS looking only at logical connections for a layout that doesn’t have power fully routed)?

Maybe what you're looking for is extracting (magic) with

extract unique notopports

or

extract unique noports

instead of just

extract unique

. (or maybe remove

extract unique

all together). I believe this essentially enables virtual connections. http://opencircuitdesign.com/magic/commandref/extract.html

Thanks for the quick reply! I gave this a shot but it didn’t seem to work. For more context, I am extracting a spice layout from GDS (and read in the LEF defining standard cells beforehand), so there are power pins defined in the layout. The Verilog netlist I’m trying to compare it to however has no power pins on any of the standard cell instantiations. I was trying to do something where I went in and removed the pins in each cell before extraction, but that didn’t seem to work:

gds noduplicates true
gds read inputs/$sc_design.gds

# Extract layout to Spice netlist
load $sc_design -dereference

select top cell
foreach cell [instance list children] {
    puts $cell
    select cell $cell
    port remove VPWR
    port remove VGND
}

select top cell
extract no all
extract do local
extract unique notopports
extract
ext2spice lvs
ext2spice ${sc_design}.ext -o outputs/$sc_design.spice

I'm not sure how to do it, but I think what you might want to do is after reading the gds, replace all the standard cells (.mag) with the LEF version (.maglef) and then remove the power ports and extract. Might be easier to add the power connections to the netlist, though (see openlane's

write_powered_verilog

in https://github.com/The-OpenROAD-Project/OpenLane/blob/master/scripts/tcl_commands/lvs.tcl).

@User: I'm a little unclear about what you're doing. You first said that the layout doesn't have power fully routed, but then you mentioned that there are power pins in the layout. In my experience, I never compare a layout against a verilog netlist without pins; it is easy enough to create a verilog netlist with the power pins included (there's a script in qflow that will convert a verilog netlist between one with and without power pins). On the rare occasion where I have a layout that does not have power connected up, I will create a quick comb structure to connect up power before extracting, even if ultimately those power connections will be replaced by others.

I meant power pins on the standard cells; not in the design itself (if that was a point of confusion). Either way though, I think you might be right that the solution is just to mock up a quick power grid rather than trying to fight Netgen and make it do something odd. Thanks both for your help!