@User: Adiabatic computing is great stuff! I remember looking into it late in my Ph.D. and it looked really interesting but I didn't have time to take on a completely different topic. I think that the existing analog function of the GPIO pad is connected to too many things for your purposes, but I can easily create a straight-through analog pad for you. I would probably want to drop 20 to 50 ohms resistance between the pad and core, and some minimal diode protection at the pad. We can talk about what your spec is for maximum current leakage at the pad. These are test chips, so there is no requirement for ESD protection, but we will want to know which chips are sensitive.

Hi Tim! Thanks for the information. Yes, straight-through analog pads would be really useful, with or without ESD (basically we just want to know that the total leakage from all the ESD circuits won't overwhelm the leakage in a chip full of active logic). For our logic style, we actually need at least 8 of these pins, not just one (for providing different phases of power-clocks). Also, adding a resistor could be a problem for us, as our goal is of course to minimize power dissipation, and so any extra series resistance in the supply path is unfavored. (If there is, however, some way to build a low-resistance "fuse" that will self-destruct at high currents, that could perhaps be an alternate way to protect the core from surges. Along with normal ESD shunts of course.)