I've done some searching around this group and I couldn't find a mention of allowed die area for the november run. Is there a number to keep in mind?

I think there latest number kicking around is on the order of 3.2mm x 5.3mm

There's a sq mm target in the original presentation, so target to that. I think it was 10 or 12 sq mm. If we get more, great

The whole chip will be (provisionally) 3.2 x 5.3, but the user area will be about 9 to 10 mm^2. That is not including the pad frame; that's the full core area you get to use. I'm aiming to keep the "management region" off to one side to keep the user area roughly square. The pads are 200um high, so the height is limited to 2.8mm, so the area you get to work with will be around 3.2 to 3.5mm wide and 2.8mm high.

Can we get bare dies or do we need to be able to integrate with a package. It would be nice to be able to put some internal bondpads to be able to test individual devices on a first run

I suspect no as the RV32 core will be using the i/o balls. I assume it will be a fan-in wlcsp and will have an epoxy coat...I suppose you might be able to pierce the epoxy and get the rdl layed out such that it's not covering key points and test that way. I believe the expected way to test individual devices will be to either use the RV32 as a test jig or connect all the devices through some sort of mux that's controlled by the RV32