@User: We do not have any pre-designed POR circuit, so I am just doing a dead-simple implementation of accumulating charge on a capacitor and feeding that into a schmitt trigger buffer. There will be a lot of corner-cutting on this shuttle run.

@Tim Edwards No worries, that's fine. I really hope I can submit a design for this run - I can factor in an external reset pin into everything, as a backup.

There is a reset pin on the chip that is passed to user space as an accessible signal (along with a clock), if you need it.

@Tim Edwards that's great. I'm sure someone has already asked, but what clock frequency?

@jrsharp: Since we have not done a final synthesis on the SoC core processor, I don't know what the external clock will be yet. However, based on the architecture, which is very similar to other chips we have done recently, I would guess that it would run at a rate of about 60-80MHz. It occurs to me now that I should probably provide a secondary clock on an independent divider, since the user area may want a clock running at a different rate from the core processor.

extra clock input would be great