Thank you for the response reference (and apologies that I didn't see it was already asked). If a design utilizes more than one clock, what is the recommended approach given the pdk environment we're using (i.e., skywater 130)? Are there going to be any pdk libraries for PLLs?

I just found this while poking around caravel harness: https://github.com/efabless/caravel/blob/release/verilog/rtl/digital_pll.v

Great, thanks!