@channel : The RTL for the Caravel harness chip is now released to the public at https://github.com/efabless/caravel ! I will be updating the documentation over the next few days, although most of what everyone needs to know can be found scattered about in various README files. The eventual go-to document will be in

doc/caravel.pdf

. At the moment, that document exists but is mostly just a collection of figures I drew up, without explanatory text. The most important thing to note is that the RTL will not be simulatable until we release the I/O pad library, which is our highest priority item at the moment. Also, we are working on the Caravel chip layout, and as soon as we have a layout for the user area showing the dimensions and pins, I will release that. We will get everyone up and running on the shuttle run designs as soon as possible!

Ooh very exciting! Is the IO pads count finalized now at 37?

Do you guys have any version of Caravel RTL that doesn't need the I/O pads modules and can be emulated on an FPGA? We want to test it with our user project design. @Tim Edwards @mshalan @Tim 'mithro' Ansell @Ahmed Ghazy

@Tim 'mithro' Ansell: The failure to release the I/O pads is now a major blocker.