@User, @User: Except that we are still pinning down what the memory arrangement is. What we are actually going to have is a somewhat complicated memory structure with something like 1kB synthesized RAM, 4kB OpenRAM block in the processor, and three 4kB blocks which are shared between the processor and user space. I will update the document when this arrangement is deemed final (we are currently looking at just how much layout each of these arrangements takes, so as to provide as much of the originally intended feature set as we can without squeezing the user space).

Ah okay, makes sense, I'll adjust my design to have some flexibility wrt how much memory is available on-chip vs off-chip. Also - just to clarify, there's no way to boot the userspace (and use its I/O) without booting the management core and using it to configure the I/O pins first, right?