There may be a problem in the open_pdk installation. I think @User is looking into it. If the LEF model ports have been modified to match the spice port order, there may have been a mixup. See https://github.com/RTimothyEdwards/open_pdks/issues/54 If you don't mind reinstalling sky130, you might try the fix I suggested for

open_pdks/common/foundry_install.py

and see if that makes a difference. Change

flabrex = re.compile('flabel[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+[^ \t]+[ \t]+([^ \t]+)')

to

flabrex = re.compile('flabel[ \t]+.*[ \t]+([^ \t]+)[ \t]*')

And then

make build-pdks

(IRCC) in the

openlane

directory. No guarantees.

Hello @Mitch Bailey! I am having the exact same issue as @Anish. I attempted to implement the fix you suggested, I cloned the latest skywater_pdk and open_pdk repos then changed the foundry_install.py file. I was unable to successfully use the "make build-pdks" command. From what directory should that be used? I tried it in my openlane install directory as well as /open_pdks/

@Bryce Readyhough (@Mitch Bailey): If you want to just make and install the tool setups, then don't cd to the openlane directory (it doesn't have a makefile), but cd to the

sky130

directory, and do

make tools-a

followed by

make install

. That will build and install the setup files for magic, openlane, etc., without rebuilding all the libraries from skywater-pdk. It will not affect any prior installation of the library files.

@Tim Edwards Thank you for the help! I ran those commands and then re ran the make command in Caravel. Unfortunately, I received the same error.

4.1. Analyzing design hierarchy..

`ERROR: Module `sky130_fd_sc_hd__clkbuf_4' referenced in module `DFFRAM' in cell

DOBUF[31]' does not have a port named 'VNB'.

@Bryce Readyhough: That's a message from yosys? Then it has to do with the contents of the liberty files. I am now checking the current state of the submodules, as I have not updated with liberty timing files recently.

@Tim Edwards Yeah that is correct. It is from part 4.1. I have posted a more complete screenshot below:

3. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/DFFRAM.v
Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/DFFRAM.v' to AST representation.
Generating RTLIL representation for module `\DFFRAM'.
Successfully finished Verilog frontend.

4. Executing HIERARCHY pass (managing design hierarchy).

4.1. Analyzing design hierarchy..
ERROR: Module `sky130_fd_sc_hd__clkbuf_4' referenced in module `DFFRAM' in cell `DOBUF[31]' does not have a port named 'VNB'.
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth_top.tcl -l /project/openlane/DFFRAM/runs/DFFRAM/logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check yosys  log file
[ERROR]: Dumping to /project/openlane/DFFRAM/runs/DFFRAM/error.log

    while executing
"try_catch [get_yosys_bin]  -c $::env(SYNTH_SCRIPT)  -l $::env(yosys_log_file_tag).log  |& tee $::env(TERMINAL_OUTPUT)"
    (procedure "run_yosys" line 18)
    invoked from within
"run_yosys"
    (procedure "run_synthesis" line 4)
    invoked from within
"run_synthesis"
    (procedure "run_non_interactive_mode" line 11)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: DFFRAM] Error 1

@Bryce Readyhough Sorry for the confusion. It should be

make build-pdk

from the openlane directory. @Tim Edwards Looks like someone has created a makefile in the top of the openlane repo that, in theory, will build the open130A pdk. https://github.com/efabless/openlane/blob/master/Makefile @Anish Did you get anything to work?

Thank you for the clarification @Mitch Bailey.

make build-pdk

did run however I am unfortunately still hitting the same error in part 4.1 of the

make

operation for Caravel.

@Bryce Readyhough Is the DFFRAM data you're using available to the public?

@Mitch Bailey it is I am currently trying to work through the example counter that comes with the Caravel repo

@Bryce Readyhough Ok. Thanks. I'll see if I get the same error.

Yep I tried the same fix and still get the error

@Anish Sorry it didn't help. You mentioned before that the LEF files were missing VNB. Is VNB still missing after the fix I proposed?

yeah still looks to be missing

@Anish as long as your PDK_ROOT is still correct openlane seems to run with no issues after an update.

Forcibly updated skywater-pdk and the latest sc_hd to the latest git versions, still having the same error

@Anish that was my experience as well

@Anish @Bryce Readyhough Not necessarily the latest version, but with the following commits

open_pdks: c2662b9
skywater-pdk: 9fcfb4c

and after the fix to

foundry_install.py

clkbuf_4

in

sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef

has the VNB pin. Does this help?

weird...

The

skywater-pdk

doesn't include the VPB, VNB pins. Those appear to be added or regenerated in the

make build-pdk

step of openlane's

Makefile

. Sorry for any confusion. @Anish @Bryce Readyhough Can you verify that

make digital_pll

works? From what I could tell, the DFFRAM.v file has issues. 1. The standard cells have power definitions which are unexpected (VGND, VPWR, VNB, VPB). 2. Even removing those, the definitions for MUX1 and other macros appear to be missing.

Digital PLL build works fine

@Anish The digital_pll design was the only one that worked for me. But then again, I haven't installed the io library yet.

@Mitch Bailey: The DFFRAM block is hand-designed and is not meant to be put through synthesis. At least that is my understanding. You can confirm that with @Ahmed Ghazy. I have not put the caravel design through synthesis myself.

@Tim Edwards Thanks for the info. the

caravel/openlane

directory contains a

Makefile

that (by default) tries to run openlane on all directories with a

config.tcl

file. Looks like this directory might contain the caravel macros. @Ahmed Ghazy Is there any documentation on how to use openlane to incorporate a RTL design and the caravel data or does that have to be done manually?

@Mitch Bailey: Was this issue before or after this commit: https://github.com/efabless/caravel/commit/8f13179aabb3377fdbb3f9f5b53eaffbfba934b0? The custom DFF block shouldn't go through yosys with the power pins.

@Ahmed Ghazy Yes, probably before; it was the Nov 10 commit bcc2544. The digital_pll was the only design I could complete, but my io libraries may have been out of date. I'm currently working on integrating CVC into openlane with @Amr Gouhar so I haven't done anything with the caravel data in the last couple days.

@Mitch Bailey: Currently you need to run things in a certain order since I kept the prerequisites loose in the Makefile. If you use the following commands in order, you should get a chip floorplan (routing is still a WIP now):

make user_proj_example
make user_project_wrapper

make digital_pll
make DFFRAM
make mgmt_core

make storage

make mgmt_protect

make simple_por

make user_id_programming

make chip_io

make caravel

You may run into issues with the RTL that I am working on locally (e.g., cell name missing the size

_1

). I will push those as soon as I can. Let me know if you have trouble running the above. I used rc5 (currentt develop branch) of openlane.

@Ahmed Ghazy I cloned and build the latest version of skywater-pdk, open-pdk, and caravel. I have the latest develop branch of openlane as well. I tried to follow the make order you posted above and ran into some issues. The first was with

make user_project_wrapper.

The issue is with the placement step. The error suggests decreasing the

init_density_penalty

value. Do you know where this value is located to adjust? I have pasted the full error below:

@Bryce Readyhough: The first one should have been

make user_proj_example

.

@Ahmed Ghazy Sorry I should have clarified I ran that one first and it ran without errors. I then ran

make user_project_wrapper

which failed with the above errors.

Hi, I had a similar problem during

make user_proj_example

, and replacing the value of

set ::env(PL_TARGET_DESNSITY)

from 0.15 to 0.2 in the config.tcl file seems to fix the problem. Is there any guidance on the choice of this target density value?