Is there a setup for doing post-synthesis simulation of caravel (including both mgmt and user-space project)? Unless I'm misunderstanding, it seems that the existing testbenches all just simulate the original verilog?

Good question

A verilog file is extracted during LVS from post-routing file.

@Anish: I am not all that familiar with where openlane puts all its working files, but gate-level simulation is mainly a matter of including the gate-level netlists. This should be controlled by "-D" option definitions passed to iverilog.

@Roomi Naqvi, @Wajeh ul hasan for post synthesis simulation.

where can I find the setup for doing behavioral simulations of caravel including my user projexample ? also there is an fpga emulation setup ?