I am trying to run the Gate-level simulation with caravel_user_project, however, it seems that the caravel RTL netlist differs from the caravel Gate-level netlist. I got this error when compiling caravel_user_project simulation with SIM=GL:

caravel/verilog/gl/caravel.v:3483: error: port ``la_oen'' is not a port of mprj.
caravel/verilog/gl/caravel.v:3483: warning: Port 16 (analog_io) of user_project_wrapper expects 29 bits, got 31.
caravel/verilog/gl/caravel.v:3483:        : Leaving 2 high bits of the expression dangling.
caravel/verilog/gl/caravel.v:3512: warning: input port clock is coerced to inout.

The RTL netlist has port 'la_oenb' while it is 'la_oen' in the GL netlist. In addition, 'make verify-wb_port' failed with SIM=GL after changing 'la_oen' in the GL netlist into 'la_oenb'. Does the GL netlist match the RTL netlist?

One reason that we separated out the user project, in addition to saving storage space, was to give us plenty of time to finish the updates on the management SoC. Right now, the caravel repository has the updated RTL, but the GL netlists still correspond to MPW-one.

Thank you very much for the information.