I have several fresh and newly generated standard ...
# shuttlep
Philipp Gühring
06/18/2021, 12:21 PMI have several fresh and newly generated standard cells for Sky130, does anyone want to take one of the cells and add it to their own design for MPW2?
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mehdi
06/18/2021, 12:51 PMHi! Is there any info about it? Tracks?
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Philipp Gühring
06/18/2021, 1:02 PMHere are the cells: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/tree/main/cells , they are using the SITE=unit sizing (not unithd which would be the default configuration in openlane)
Philipp Gühring
06/18/2021, 1:03 PMI am currently doing the final review and will provide more information soon.
Philipp Gühring
06/18/2021, 6:23 PMHere is the buildreport for the cells (and some more, I only used the DRC clean ones): https://pdk.libresilicon.com/dist/StdCellLib_20210618/Catalog/buildreport.html
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mehdi
06/18/2021, 6:26 PMThanks, did you use those in openlane? are you taping out ROs? I asked one of the students to try these out. But I am not sure if they are meant for speed, density or power/leakage?
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Philipp Gühring
06/18/2021, 6:31 PMYes, this is my project to try as many of them as I have IO: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/ They are meant for automatic generation (no human in the loop), low density. But since I can't try all of them, due to limited IO, I was hoping others could try to put individual cells on their existing designs as well to fill up their design.
Philipp Gühring
06/18/2021, 6:32 PMI am using them in openlane, but I placed them as pre-placed macros, I didnt synthesize digital logic with them yet, I just placed them individually and wired them up to the IOs and the LogicAnalyzer. Synthesizing digital logic is planned for the next tapeout.