@Dan Fritchman: Trying to keep the explanation short, but basically the Caravel work done in OpenLane was pushing the boundaries and some layout was just sort of hacked in. . . one of those hacks caused a couple of internal signals to fail to get routed, and the block was not re-verified through LVS (or possibly was, but there was also an issue at the time with a version of netgen that ignored disconnected ports). Fortunately we were able to connect the missing routes all on the metal2 layer only, and we found the issue before the metal masks were made (the masks are done in two sets, so the front-end masks had already been made and the wafers had been started on the front-end process). So there's less of a delay than you might expect, since the chips were already in manufacture, and we only needed to correct one mask. It took long enough to get the ECO through that there's probably some impact, but it's not like it was holding up the whole shuttle run.