Hi, I'm trying to use OpenLane with the following module of my project: https://github.com/theatomb/Elpis-Light-MPW3/blob/main/verilog/rtl/elpis/regfile.v with the following config: https://github.com/theatomb/Elpis-Light-MPW3/blob/main/openlane/regfile/config.tcl The workflow stops at step 15 with the following messages and then it raises an error:

[INFO GRT-0101] Running extra iterations to remove overflow.

[INFO GRT-0103] Extra Run for hard benchmark.

How can I reduce congestion and overflow with that very simple module (even having a big die and low density)? What is wrong in my Verilog code or config file?? Thank you!

Probably you want to post that question in #openlane

@User Well, I managed to do that by commenting out the

set ::env(PL_BASIC_PLACEMENT) 1

.

@User it worked! Thanks a lot😃