Antenna Summary:
Source: /project/openlane/computer/runs/computer/reports/routing/38-antenna.rpt
Number of pins violated: 107
Number of nets violated: 103
[INFO]: check full report here: /project/openlane/computer/runs/computer/reports/final_summary_report.csv
[WARNING]: There are max slew violations in the design at the typical corner. Please refer to /project/openlane/computer/runs/computer/reports/routing/23-spef_extraction_sta.slew.rpt
[ERROR]: There are hold violations in the design at the typical corner. Please refer to /project/openlane/computer/runs/computer/reports/routing/23-spef_extraction_sta.min.rpt.
[INFO]: Calculating Runtime From the Start...
[INFO]: flow failed for computer/2021.10.30_11.17.19 in 12h43m8s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: computer
Run Directory: /project/openlane/computer/runs/computer

Hi, after updating OpenLANE, I get the above error when I build my design and it crashes. What is a typical corner and how do I solve it? The error occurs when I run

make computer

. My project repo is here: https://github.com/cpu-dev/caravel_jacaranda-8 My project is here: https://efabless.com/projects/413 Thank you. Posted in #general

@User Simulation 'corners' refers to operating conditions and process fluctuations, I believe. 'typical' is typical conditions and device speeds. I've also seen 'ss' or 'ff' for slow nmos/pmos or fast nmos/pmos. As to how to solve this timing issue, I'd suggest looking at the document recommended in this announcement. https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1635567450092200

@User Thank you so much for the explanation, I understand now. I'll take a look at the documentation.